As the quantum computing sector continues to focus on improving fidelity and error rates, Riverlane has announced its dedicated ASIC demonstrator decoder chip for predicting and correcting errors, and published its decoder IP and a paper on resource-efficient error correction for quantum computers.
The moves represent a significant step forward in the company’s ongoing effort to build out the quantum error correction stack that Riverlane and others have argued that every quantum computer will need to achieve useful scale.
Steve Brierley, CEO and founder of Riverlane, said, “We’re entering a new era of quantum computing where we begin tackling the technology’s defining challenge – the need to scale from a few hundred quantum operations to a trillion quantum operations without failure.
Riverlane plans to demonstrate the DD0A ASIC, the first in its planned Decode ASIC family, in live hardware in the fourth quarter of this year, while the publishing of the DD1 decoder IP allows for quick prototyping and integration, meaning that the error correction technology can be deployed on an FPGA for quantum computer makers to incorporate into their own hardware.
“We implement our decoder on both an FPGA and ASIC, the latter ultimately being necessary for any cost-effective scalable solution,” the company’s research paper stated.
The new solutions can be integrated into superconducting, trapped ion, and neutral atom quantum hardware, Riverlane said.
Brierley added, “We are now implementing quantum algorithms on actual hardware. Crucially, Riverlane has found a balance to address all the metrics required to create a real-world decoder to solve real-world problems – making our decoder the most powerful decoder available.”
Riverlane raised $18.7 million in new funding in April of this year.
Dan O’Shea has covered telecommunications and related topics including semiconductors, sensors, retail systems, digital payments and quantum computing/technology for over 25 years.
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- Source: https://www.insidequantumtechnology.com/news-archive/riverlane-unveils-decoder-chip-in-step-toward-error-correction-stack/
