Recentely a new DPU IP product guide (PG338) was been published on Xilinx.com. You can be download it here.  

Alternatively, visit the AI Edge resources page and downloaded from the documentation link shown below.

This document consists of two parts. The first part provides details of the DPU IP hardware architecture, register space, configuration, clock and reset etc.

The second part walks through the whole development flow –  from adding IP into a repository all the way down to generating the BOOT.BIN with Vivado & Xilinx SDK. It also includes an example design showing how to integrate DPU IP to run Resnet50 on the ZCU102 platform.

This makes it easier and less error prone for our users to integrate DPU IP into custom platforms based on Xilinx SoC’s.